Investigation of the Performance of Carbon Nanotube FET for Analog Circuits

Carbon Nanotube FET technology is a new promising technology for high speed digital applications. This paper investigates optimizing Analog Circuits architecture to take advantage of this technology in mixed mode ICs and point at the optimum topology for CNFETs for the first time. It was found through simulations that the optimum topology for high-bandwidth analog circuits is obtained by using architecture which avoids loading by the high CNFET gate capacitance in the main signal path at high impedance points. Low junction capacitances of CNFET and high transconductance (gm) compared to silicon MOSFET indicates that high gain-bandwidth can be obtained by using CNFET. Simulations indicate low voltage operation (0.5V) is possible using CNFET technology and also high temperature operation (> 200C) is possible. Monte-Carlo simulations indicate that device matching of important CNFET parameters such as nanotube diameter, channel length, source/drain doping are important to get consistent results.